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PT Pericom Technology Inc.
Features
Compliant to Bluetooth Specification v1.2 Seamless interface to PT8R1002 (BlueRFTM RF transceiver) High speed UART, USB 1.1 interface with hub/devices and host function, up to four channels 8KHz PCM / CVSD codec, 16/18/20/24-bit I S audio input/output and SPDIF input/output interface, 2 channel digital AMP interface Integrated 128MHz PTI own hybrid RISC and DSP PiCOII embedded and processor 48-bit with 24-bit and multiplication accumulation
2
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC General Descriptions
The PT8R1202 is a part of the PTI Bluetooth product family. It is a DSP processor with the functionality of both baseband controller providing the BluetoothTM functionality for high data rate, short-distance wireless communication in the free 2.4GHz ISM band and digital audio decoder such as MP3 or AC3. Together with PT8R100X 2.4GHz radio transceiver IC and an external flash memory, it provides a fully compliant Bluetooth system for data and voice communications. PT8R1202 consists of BlueRFTM RXMODE2/3, 3-wires radio interface, BluetoothTM baseband and bit processor, PTI proprietary 32-bit hybrid RISC/DSP embedded processor with 48bit resolution, and USB / UART / PCM / DAC / I2S / SPDIF / SMC standard interfaces. The on-chip 32-bit hybrid RISC/DSP embedded processor is powerful enough to support full rate Bluetooth data communications as well as full rate digital audio decoding and includes large enough embedded SRAM up to 128KByte to support several applications without external memory, which results in cost-effective and low-power consumption systems. In combination with PTI own optimized BluetoothTM baseband, embedded protocol stacks and audio decoder firmware, it provides a complete cost-effective SOC embedded solutions such as portable MP3 decoder, wireless high quality speaker system or headset.
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128KByte on-chip SRAM enough to support several digital audio and speech codecs On-chip implementation of BT qualified Link Controller, Link Manager, HCI, L2CAP, RFCOMM and several profiles such as Headset, SPP, OBEX, AV profiles, etc. Software development kit and source code licenses available for qualified embedded stacks and DSP firmware for popular digital audio and speech codecs Single reference clock for system, USB, audio sub system 0.18um CMOS technology
Application
Bluetooth portable audio players Stereo audio headset with HSP/HFP function Multi-functions USB dongle such as Bluetooth, USB audio device, USB Flash storage, etc. Wireless high quality digital audio streaming system for DVD/PC speaker
PT0137(08/04) 1
Ver:4
PT Pericom Technology Inc.
Ordering Information
Device Type Normal LQFP144 Pb(Lead) free PT8R1202 Normal fpBGA144 Pb(Lead) free Package Size
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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20 x 20 x 1.4mm
10 x 10 x 1.4mm
Shipment Method Tray T&R Tray T&R Tray T&R Tray T&R
Order Number PT8R1202F PT8R1202FX PT8R1202FE PT8R1202FEX PT8R1202ND PT8R1202NDX PT8R1202NDE PT8R1202NDEX
Block Diagram
MEM IF MMU & DMA V6PB Bridge
NAND Flash Controller GPIO (up to 56) Speech Codec I/F I2S Input, SPDIF Input I2S Output, SPDIF Output
User Applications Flash (2MB)
Hybrid 32 -bit RISC MCU & 24-bit DSP Core (V6@PiCOII -DSP,128MHz)
I-Cache 16KB YMEM2 16KB XMEM2 16KB
20bit address, 16bit data
I/O1 (2MB) (IDE/ Ethernet)
SRAM (2MB) (option)
I/O0 (2MB) (LCD)
XMEM0 32KB
YMEM0 32KB
XMEM1 16KB
YMEM1 16KB
PC Phone PDA
serial
USB (Multi-function Devices or Host) High speed UART
System registers
Interrupt / Timer
NAND GPIO
NAND Flash (2x2Gb)
DSP library Network library File System library PTI Stacks & Profiles Third party Stacks & Profiles HCI BB/LM
serial
HOST, Off-chip Debugger
JTAG
OSC
On chip debugger RTC Power Mng .
Bluetooth Controller Bit Processor (BT1.2 compliant)
serial
Speech Codec
32.768kHz
OSC
SYSPLL AUDPLL
Multi-mode RF transceiver I/F (BlueRF RXMODE2/3 3-wires RF I/F)
Serial
Stereo Audio ADC Stereo Audio DAC
RTOS (VPOS TM, eCos TM)
PT8R1202 software
serial
12/13/16/19.2MHz Bluetooth Radio PT8R1002
BlueRF RXMODE2
PT0137(08/04) 2
Ver:4
PT Pericom Technology Inc.
Product Description
Bluetooth is an open specification for short-range data communications. It operates in the globally available 2.4 GHz to 2.5 GHz ISM free band. Fast frequency hopping (1600 hop/s), 79 available channels (2.402 to 2.480 GHz), and a maximum 1 Mbit/s GFSK modem are allowed. The PT8R1202 consists of a Bluetooth baseband hardware, on-chip 128MHz hybrid embedded RISC / DSP processor and peripheral interface block. The PT8R1202 focuses on audio streaming to distribute audio content of high-quality in mono or stereo on ACL channels of Bluetooth. Since PT8R1202 is highly integrated SOC solution to support the Advanced Audio Distribution Profile(A2DP) defined in Bluetooth as audio streaming application with minimum BOM, the minimum required external devices are just PT8R100X 2.4GHz radio transceiver IC, external antenna, crystal, and minimum 256KB flash memory for program code. Bluetooth baseband hardware Bluetooth baseband hardware consists of modem control, packet processing hardware, and on-chip microcontroller interface. Modem control part generates the control signal for modem and RF block and transmits or receives data with modem. PT8R1202 supports BlueRFTM RXMODE2/3 Bluetooth radio interface with uni/bi-directional and JTAG/DBUS serial interface like PT8R1000 or PT8R1001 PTI Bluetooth radio transceiver. In RXMODE3, SYNCWORD correlator is located in radio transceiver, SYNCWORD detect signal feeds from external radio transceiver. In RXMODE2, SYNCWORD correlation is processed in PT8R1202, SYNCWORD detect signal feed to external radio transceiver to timing adjustment of modem. In additional to BlueRFTM interface, PT8R1202 supports BlueQTM interface with SBI serial interface. Packet processing for Bluetooth is implemented by a dedicated hardware for a low power solution whilst providing the required data throughput. The function implemented in hardware include : forward error correction, header error control, cyclic redundancy check, encryption, and data whitening. On-chip microcontroller interface generates interrupt signal to on-chip interrupt handler and processes DMA operation with 16KB internal memory(XMEM2) which is shared with on-chip microcontroller. During radio transmission this block constructs a packet from header information and payload data/voice taken from a ring buffer in XMEM2 which is previously loaded by software. For radio reception, this block stores the packet header and the payload data in the appropriate ring buffer in XMEM2, which is indicated by software. After the completion of reception, this block generates interrupt signal to on-chip interrupt handler. This architecture minimizes the interventions required by the processor during packet transmission and reception.
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
Hybrid embedded RISC / DSP processor To satisfy multimedia data streaming through wireless connectivity like Bluetooth, the embedded processor used in portable system must provide highly energy-efficient operations, due to the importance of battery weight and size without compromising high performance when the user requires it. The functions required in this application are classified into two computations such as MCU operation and DSP operation. The former performs all functions associated with user interface as well as real-time communication protocols and the latter performs all signalprocessing and multimedia functions. The on-chip embedded processor in the PT8R1202 is based on PTI proprietary V6 processor(PiCOII-RISC/DSP), which is optimized to accelerate both two computations for low power and high performance embedded processing. Its instruction set is optimized not only for general embedded processing but also DSP signal processing specially used in audio and speech code. This hybrid embedded RISC/DSP processor supports 24-bit multiplication and 48-bit accumulator with DSP functionality such as saturation and rounding. Also, it supports SIMD features, which results in high performance in 16-bit speech applications. To support low power consumption, on-chip processor adopts programmable dynamic clock control, reduces the complexity of embedded RTOS optimizing for both Bluetooth connectivity and audio streaming, and minimizes external I/O access with several techniques. Default operation frequency is 96MHz at boot and it can be increased to 128MHz entering into turbo mode. There are four global power states provided in PT8R1202 such as active state, sleep state, deep sleep state and power-off state. In active state, processor can change the processor clock between normal operation clock, a half of one, and a third of one. For example, if processor operates in turbo mode, it can change processor clock between 128MHz, 64MHz and 42MHz. Also, during the execution of "idle" instruction, it cuts down the processor clock without interrupting I/O device operation. In sleep state, the clock of all processor and I/O device except RTC is disabled. In sleep state, processor can be waked up quickly by RTC time-out event or external trigger signal since on-chip PLL is still working in order to fast response. Deep sleep state is the same of sleep state except on-chip PLL is off also. Since on-chip PLL is off in deep sleep state, the power consumption is reduced very much but requires more latency during wakeup. To minimize the access of external flash memory for code, PT8R1202 includes on-chip 16KB instruction cache. In addition to instruction cache, frequent access code or time critical code is dynamically located on scratch-pad memory of internal X/YMEM region. It is possible to allocate up to 96KB as scratch-pad memory in order to reduce external memory access for low power and high performance Bluetooth digital audio streaming system. Total 128KB internal SRAM is integrated large enough to support both on-chip Bluetooth stack and audio application without external memory, which results in cost-effective and low-power consumption systems. Internal SRAM Ver:4 3
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PT0137(08/04)
PT Pericom Technology Inc.
consists of six types memories : XMEM0, XMEM1, XMEM2, YMEM0, YMEM1, and YMEM2. All memories can be byte accessible as general purpose data memory. Some memories such as XMEM2 and YMEM2 have special usage. XMEM2 is used as 16KB memory for communication with Bluetooth baseband hardware or USB, and YMEM2 is used as 16KB memory for communication with audio data buffer for stereo PCM output. PT8R1202 can boot from NOR type flash and NAND type flash memory. With NOR type flash memory, code can be cached into internal instruction cache in order to execute code at high frequency and reduce power consumption of frequent memory fetch. With NAND type flash memory, both code and data are stored same memory, which results in the reduction of system BOM and form factor. If PT8R1202 boots from NAND flash, the configuration of the internal instruction cache is optimized to support NAND flash efficiently. Software development environment The PT8R1202 supports high-level programming development with our optimized C compiler based on GCC and intrinsic library functions to maximize the software development productivity. The system software to support application software development includes C-compiler, multi-level instruction set simulator, performance analyzing profiler, memory configuration optimizer and power monitor. Specially, our C compiler supports automatically collaboration mechanism between compiled general code and hand-written DSP libraries to maximize the utilization of V6 advanced features. To reduce the system developing cost, PTI provides performance optimized DSP library for enabling several multimedia standards with our own developing skill for multimedia application. This library supports several standards such as MPEG-1/2 layer I, II, III audio decompression, Dolby Digital decompression, WMA, SBC codec, G.723.1/G.728 speech codec, etc. Advanced audio streaming on Bluetooth PT8R1202 supports advanced audio streaming using the advanced audio distribution profile(A2DP) defined in Bluetooth. This profile is used by devices to distribute audio content of high-quality in mono or stereo on ACL channels, as well as Bluetooth audio which indicates distribution of narrow band voice on SCO channel. PT8R1202 support several codecs in A2DP such as low complexity subband codec(SBC), MPEG-1,2 audio, or WMA. This advanced audio streaming feature of PT8R1202 can be used several audio system with Bluetooth connectivity between portable audio player and headphone, high-quality audio system and surround speaker, or portable speech recorder and microphone. For supporting A2DP, PT8R1202 embeds all Bluetooth stack such as baseband, LMP, L2CAP, SDP, AVDTP(A/V Distribution Transport Protocol) and AVCTP(A/V Control Transport Protocol). As well as A2DP, PT8R1202 supports cordless phone or dial-up networking using RFCOMM, TCS/BIN protocol and profiles. PT0137(08/04) 4
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
Peripheral Interface block PT8R1202 has several peripheral interface such as off-chip memory interface, USB interface, UART interface, PCM interface, I2S and SPDIF interface, JTAG interface, Flash Memory/Card interface, and up-to 59-general purpose programmable I/O(GPIO) interface. All peripheral devices are connected to on-chip microcontroller via internal peripheral bus(V6PB), which is compatible with Advanced Peripheral Bus(APB) from ARMTM Off-chip memory interface supports 4 devices concurrently such as flash memory, SRAM, and I/O for code and data. It supports 2MB address space and 16bit data with byte access functionality. The access timing for each device can be programmable by software. Also, PT8R1202 supports external I/O with explicit wait signal such as PCMCIA card. USB interface supports both 12Mbps and 1.5Mbps serial data communication conforming to universal serial bus standard version 1.1. It supports both device and host side operation and all operation modes such as bulk, interrupt, control and isochronous mode. It consists of one control end-point, four receiver end-points and four transmit endpoints, each of which has dual 64bytes FIFO except control end-point and supports bulk, interrupt, and control, and two pair of end-points which supports isochronous mode up to 1023bytes. On-chip UART supports programmable baud rate up to maximum 1.84MBaud serial communication and fully programmable serial interface such as flow control and bit format. It includes separate 16-byte transmit and receiver FIFOs to reduce CPU interrupts. PCM interface supports the external PCM codec with CVSD Bluetooth codec functionality. For the external PCM codec, it support 8-bit A/u-law PCM and 13- or 14-bit 8KHz linear PCM in both master or slave mode. For 8-bit A/u-law format, it supports one, two and four channels simultaneously. Audio output interface supports I2S digital audio interface, SPDIF digital audio interface. For external DAC, it supports 32, 44.1, or 48KHz sampling frequencies with the programmable bit resolution up to 24bit. All sampling frequency can be generated both from on-chip audio PLL or external clock source. Audio input interface supports both I2S interface and SPDIF interface with 32, 44.1, or 48kHz sampling frequencies. For slave mode in which all control signals come from external, I2S interface can support up to 192kHz sampling frequency. PT8R1202 supports the dedicated hardware interface to SmartMediaTM flash memory(NAND type) or card. Without the occupation of the CPU resource, it supports DMA transfer for SmartMediaTM interface to achieve fast read/write operation. At SMC boot mode, PT8R1202 can boot from SMC without normal parallel flash of NOR type. PT8R1202 provides 59-bit programmable, bi-directional IO(GPIO) which are shared with dedicated pins in order to reduce pins. GPIO signal can be used as key-pad input, MMC/SDCard/Memory StickTM interface, or LCD interface. Ver:4
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PT Pericom Technology Inc.
PT8R1202 supports standard JTAG interface for both boundary scan and communication channel with PTI enhanced on-chip hardware debugger controller. Using onchip debugger controller, off-chip debug handler or external host can access internal peripheral device registers, external
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
memory interface, and executes real-timing hardware debugging and monitoring of on-chip embedded RISC processor. Also, external host can communicate on-chip processor through JTAG with on-chip hardware managed channel buffer.
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PT0137(08/04) 5
Ver:4
PT Pericom Technology Inc.
Pin Descriptions
Pin Name PIN I/O TYPE
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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Description
DI(Digital Input, 3.3V), DO(Digital Output, 3.3V), DB(Digital Bidirectional, 3.3V), DP(Digital Programmable, 3.3V) DCP(Digital Core Power, 1.8V), DPP(Digital Peripheral Power, 3.3V) DCG(Digital Core Ground), DPG(Digital Peripheral Ground) AAI(Analog Audio Input, 3.3V), AAO(Analog Audio Output, 3.3V), AAB(Analog Audio Bidirectional, 3.3V) ACI(Analog Core Input, 1.8V), ACO(Analog Core Output, 1.8V), ACB(Analog Core Bidirectional, 1.8V) AAP(Analog Audio Power, 3.3V), AAG(Analog Audio Ground) ACP(Analog Core Power, 1.8V), ACG(Analog Core Ground)
BLUETOOTH INTERFACE : 12 TXACTIVE / GPA[0] D4 RXACTIVE / GPA[1] C1 TXDATA_EN / GPA[2] E2 TXDATA / GPA[3] D1 RXDATA / GPA[4] E3 SYNCDECTECT / GPA[5] E1 DATACLK / GPA[6] F1 RFRESET / GPA[7] F3 BLUERF_TCK / GPA[8] F2 BLUERF_TMS / GPA[9] G3 BLUERF_TDI / GPA[10] G1 BLUERF_TDO / GPA[11] G2 CLOCK SIGNAL INTERFACE : 6 XTALIN J8 XTALOUT L9 PLL_MD1 PLL_MD0 M10 M11 DO/ DP DO / DP DO / DP DB / DP DI / DP DB / DP DI / DP DO / DP DO / DP DO / DP DB / DP DI / DP DI DO DI DI / DO DI DO / DP DI DI / DP DI DI / DP DI / DP DI / DP DI / DP DO / DP DO DB DO DO DO / DP DO / DP DO DO / DP DO / DP DO / DP DI / DP DO / DP DI / DP DO / DP DO / DP DB DB active high active high active high serial data serial data active high clock active high clock serial data serial data serial data clock clock control control control pin clock active low control pin control pin clock serial data active low serial data serial data bus bus active low active low active low active low active low active low active low active low control pin serial data serial data active low active low serial data serial data transmitter enable receiver enable timing reference of valid data transmit data receive data indication of SYNC word detection Phy reference data clock Reset signal for external radio transceiver a serial register interface clock control signal of Phy's TAP controller Phy control register serial data output Phy control register serial data input Crystal input for on-chip PLL (see note1) Crystal output PLL mode control (see note1) External, test clock input (see note1, 2) PLL mode control (see note1) Manufacturing test mode (see note2) External clock source select signal (see note1,2)
clock out divided by a third of internal system clock (see note1)
PLLSEL L10 CLKOUT / GPB[0] L7 TEST & DEBUG INTERFACE : 9 RESET K8 BTMD[1:0] M7, J7 SCAN_EN C5 JTAG_TCK / GPC[4] M8 JTAG_TMS / GPC[5] K7 JTAG_RST / GPC[6] L8 JTAG_TDI / GPC[7] K9 JTAG_TDO / GPC[8] M9 EXTERNAL MEMORY INTERFACE : 45 (see note4) MEMA[19:0] (see note5) MEMD[15:0] WEB C10 REB C12 UBE / GPB[1] D11 LBE / GPB[2] D10 FLASHCSB / GPB[3] D12 SRAMCSB / GPB[4] E10 IOCSB0 / GPB[5] E11 IOCSB1 / SM_CSB1 / GPB[6] E12 IOWAIT / GPB[7] F10 UART & USB INTERFACE : 6 UARTTX / GPC[0] H3 UARTRX / GPC[1] H1 DIGAMP_L / UARTRTS / H2 AUDISCLK / GPC[2] DIGAMP_R / UARTCTS / J4 AUDILRCLK / GPC[3] D+ B4 DA4
reset signal boot mode (see note2) manufacturing test (see note3) JTAG clock signal JTAG test mode signal JTAG reset signal JTAG serial input data JTAG serial output data address bus for external memory data bus for external memory write enable signal for external memory read enable signal for external memory upper byte enable (see note6) lower byte enable (see note6) chip select for external flash memory chip select for external SRAM memory chip select for external I/O device0 chip select for external I/O device1 (see note7) IO wait cycle extension indication signal UART serial transmit data / USBOE UART serial receive data / USBSPEED UART RTS(Ready To Send) signal / USBVPO AUDISCLK / DIGAMP_L (see note8) UART CTS(Clear To Send) signal / USBVMO AUDILRCLK / DIGAMP_R(see note8) USB D+ USB D-
PT0137(08/04) 6
Ver:4
PT Pericom Technology Inc.
Pin Name PIN I/O DIGITAL AUDIO INTERFACE : 9 PCMOUT / GPD[0] J3 DO / DP PCMIN / GPD[1] J1 DI / DP PCMSYNC / GPD[2] J2 DP PCMCLK / GPD[3] K1 DP AUDSCLK / GPD[4] K2 DP AUDLRCLK / GPD[5] L1 DP AUDOUT / GPD[6] L2 DO / DP AUDMCLK / GPD[7] M1 DP AUDIN / SPDIFIN/GPD[8] K3 DI / DP ANALOG AUDIO INTERFACE : 6 (see note9) MIC_IN B2 AAI MICGS A1 AAO VMID C3 AAO VREF C2 AAO EARA C4 AAO EARB B1 AAO SMARTMEDIA INTERFACE : 14 SM_CSB / GPE[0] L3 DO / DP SM_CLE / GPE[1] M2 DO / DP SM_ALE / GPE[2] M3 DO / DP SM_WE / GPE[3] K4 DO / DP SM_OE / GPE[4] M4 DO / DP SM_RB / GPE[5] L4 DI / DP (see note10) SM_DATA[7:0] /GPF[7:0] DB GPIO INTERFACE : 7 GPG[0] / IRQ0 / SSM1 D6 DI / DP GPG[1] / IRQ1 B6 DI / DP GPG[2] / WAKEUP C6 DI / DP GPG[3] / SSM0 A5 DO / DP GPG[4] / CLK32K D5 DB / DP SPDIFO / GPG[5] B5 DO / DP POWER SUPPLIES : 31 SPLL_VCC(1) L11 ACP SPLL_GND(1) M12 ACG APLL_VCC(1) D3 ACP APLL_GND(1) D2 ACG ACODEC_VCC(1) A2 AAP ACODEC_GND(2) A3, B3 AAG (see note15) VCC(6) DCP (see note16) VCC_GND(6) DCG (see note17) VPP(6) DPP (see note18) VPP_GND(6) DPG TYPE serial data serial data clock clock clock clock/ serial data clock serial data analog analog analog analog analog analog active low active low active low active low active low control pin bus active high active high active high clock signal signal power ground power ground power ground power ground power ground
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
Description PCM 8kbps data out PCM 8kbps data input PCM 8KHz frame synchronization signal PCM bit data clock (128/256) audio serial data bit clock(64*fs) audio left/right sync clock(fs) audio serial data output audio oversampled clock(256/384*fs) audio serial data input Reserved Reserved Reserved Reserved Sleep crystal(32.768kHz) XTALIN Sleep crystal(32.768kHz) XTALOUT Smartmedia chip select Smartmedia command latch enable Smartmedia address latch enable Smartmedia write enable Smartmedia read enable Smartmedia ready signal Smartmedia data/address bus external interrupt request0 (see note11) external interrupt request1 / USBVPI external wake up signal (see note12) / USBRCV Size indicator at Smartmedia boot (see note11) / USBVMI External RTC clock(32kHz) input (see note13) SPDIF output / USBSUSPND (see note14) supply for system PLL (1.8V) ground for system PLL supply for audio PLL (1.8V) ground for audio PLL supply for combo audio codec (3.0V) ground for combo audio codec power for digital core block (1.8V) ground for digital core block supply for digital peripheral blocks (3.3V) ground for digital peripheral blocks
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Note :
1. PT8R1202 use two main clocks for core operation and peripheral operation. Both clocks can be generated from on-chip PLL or individually pumped from external clock source. The clock for processor operation, named CLKSYS, can be variable by application requirement or dynamic power management, but the clock for peripheral operation must be fixed as 48MHz for USB and audio interface and 32MHz for others. The PLL in the PT8R1202 supports 12MHz, 13MHz, 16MHz, or 19.2MHz as reference clock. Following table shows the configuration of PT8R1202 clock generation block. For using internal clock from on-chip PLL, PLLSEL must be set "0". When using internal clock from on-chip PLL, PT8R1202 can change the operating frequency of on-chip processor up to 128MHz turbo mode. The default operation mode is normal execution at 96MHz operating frequency and it can be changed into turbo mode by software. However, in the case of using external clock source, it does not support turbo mode.
PT0137(08/04) 7
Ver:4
PT Pericom Technology Inc.
Table 1. PLL mode set value for setting core frequency
XTALIN 12MHz 13MHz 16MHz 19.2MHz Don't use Don't use PLL_MD1 Low Low High High 96MHz TESTCLK PLL_MD0 Low High Low High Low High PLLSEL Low Low Low Low High High
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
CLKOUT 32MHz 42.7MHz 32MHz 42.7MHz 32MHz 42.7MHz 32MHz 42.7MHz 32MHz TESTCLK CLKSYS 96MHz 128MHz 96MHz 128MHz 96MHz 128MHz 96MHz 128MHz 96MHz TESTCLK Comment Normal mode Turbo mode Normal mode Turbo mode Normal mode Turbo mode Normal mode Turbo mode Normal mode TEST mode
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2. If both PLL_MD0 and PLLSEL are high, the operation mode of PT8R1202 changes into TEST mode. This mode is used only for manufacturing test purpose. In TEST mode, the boot mode will be used as indication of specific test mode. In normal mode, the boot mode indicates the source of boot code to be fetched first PC.
Table 2. Boot mode set value for indicating the source of boot code fetch in normal mode
BTMD[1:0] 0 1 2 3 Name Flash Debug reserved NandFlash Comment Boot from external memory using FLASHCSB[0] signal Wait for debug command through JTAG Bood from NandFlash using smart media interface The size of NandFlash is indicated by SSM pin. See note7 for more information. Comment Full scan test mode (manufacturing test purpose) Analog audio external test mode (debugging purpose) Audio left DAC and ADC test mode (manufacturing test purpose) Audio right DAC and ADC test mode (manufacturing test purpose)
Table 3. Boot mode set value for indicating the source of boot code fetch in test mode
BTMD[1:0] 0 1 2 3 Name SCAN test Codec test Codec0 test Codec1 test
3. This pin should be low for normal operation. It is used only in manufacturing test. 4. PIN of MEMA[19:0] : A6, B7, A7, C7, D7, B8, A8, D8, A9, C8, D9, A10, B9, C9, B10, A11, A12, B11, B12, C11 5. PIN of MEMD[15:0] : F11, F12, G11, G12, H12, G10, H11, H10, J12, K12, J9, J11, J10, L12, K11, K10 6. In non byte access device such as flash memory(x16), these pin will be not connected. 7. This pin can be programmed to access the second NAND flash chip in addition to SM_CSB signal. With this pin, PT8R1202 can support up to 4 Gb(512MB) NAND flash directly. 8. These pins can be used as multiple purposes by programming such as digital AMP output, UART flow control signal and alternative I2S input. From R2.4, the default direction and signal usage is changed. The default configuration is the output of internal digital amplifier. For the case of alternative I2S input mode, the sampling frequency of I2S input can be different to that of I2S output. 9. Internal audio codec is not recommended to use for both voice and audio. Instead of internal stereo sigma-delta DAC, we recommend to use external voice and audio codec. From R2.6, EARA and EARB PAD are only dedicated to oscillator PAD for external sleep crystal. 10. PIN of SM_DATA[7:0] : K5, J5, M5, L5, K6, M6, J6, L6 11. These pins is only used at NandFlash boot mode. If BTMD is "11" which means on-chip processor boots from NandFlash, these pins are used as size indication of external NandFlash. After the completion of boot, it is used as GPIO. Otherwise, it is always used as GPIO. 12. This signal can be programmed for embedded processor to be waked up from sleep or deep sleep power state. 13. Instead of dividing clock from XTALIN, this pin can be used as the low oscillator clock source as programming for extremely low power consumption in stand-by state. 14. From R2.4, the default direction of this pin is output as SPDIF output signal. 15. PIN of VCC : G4, H4, H5, H6, H7, H8 16. PIN of VPP : F5, F6, F7, F8, G9, H9 17. PIN of VCC_GND : E4, F4, G5, G6, G7, G8 18. PIN of VPP_GND : E5, E6, E7, E8, E9, F9
PT0137(08/04) 8
Ver:4
PT Pericom Technology Inc.
Package Diagram
10mm 1 A B C D E F
MICGS
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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The circuits is packaged with 144pin FPBGA and LQFP package. The body size of FPBGA is 10x10mm and the body size of LQFP is 20x20mm. Following figure shows the top view of the package.
2
3
4
D-
5
GPG3
6
MA19
7
MA17
8
MA13
9
MA11
10
MA8
11
MA4
12
MA3
CODEC CODEC VCC GND CODEC GND VMID APLL VCC GPA4
EARB MICIN
D+
GPG5 GPG1 SCAN GPG2 EN GPG4 GPG0 VPP GND VPP VCC GND VCC VPP GND VPP VCC GND VCC
MA18
MA14
MA7
MA5
MA2
MA1
GPA1
VREF APLL GND GPA2
EARA
MA16
MA10
MA6
WEB
MA0
REB
GPA3
GPA0 VCC GND VCC GND VCC
MA15 VPP GND VPP VCC GND VCC
MA12 VPP GND VPP VCC GND VCC XTAL IN RST
MA9 VPP GND VPP GND VPP
GPB2 GPB1
GPB3
GPA5
GPB4 GPB5
GPB6
GPA6
GPA8
GPA7
GPB7 MD15
MD14
10mm
MD10 MD13 MD12
G GPA10 H J K L M
GPC1
GPA11 GPA9
GPC2
GPC0
VCC
VPP
MD8
MD9
MD11
GPD1
GPD2
GPD0
GPC3
GPF6
GPF1 BTMD0
MD5
MD3
MD4
MD7
GPD3
GPD4
GPD8
GPE3
GPF7
GPF3
GPC5
GPC7 XTAL OUT GPC8
MD0 PLL SEL PLL MD1
MD1 SPLL VCC PLL MD0
MD6
GPD5
GPD6
GPE0
GPE5
GPF4
GPF0
GPB0
GPC6
MD2 SPLL GND
GPD7
GPE1
GPE2
GPE4
GPF5
GPF2 BTMD1 GPC4
MICGS AGNDC VREF EARA EARB APLL VCC APLL GND TXACTIVE(GPA[0]) RXACTIVE(GPA[1]) TXDATA_EN(GPA[2]) TXDATA(GPA[3]) RXDATA(GPA[4]) SYNCDETECT(GPA[5]) DIG GNDC DIG VCC DATACLK(GPA[6]) RFRESET(GPA[7]) BLUERF_TCK(GPA[8]) BLUERF_TMS(GPA[9]) BLUERF_TDI(GPA[10]) BLUERF_TDO(GPA[11]) DIG VPP DIG GNDP UARTTX(GPC[0]) UARTRX(GPC[1]) UARTRTS(GPC[2]) UARTCTS(GPC[3]) PCMOUT(GPD[0]) PCMIN(GPD[1]) PCMSYNC(GPD[2]) PCMCLK(GPD[3]) DIG VCC DIG GNDC AUDSCLK(GPD[4]) AUDLRCLK(GPD[5]) AUDOUT(GPD[6])
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
MIC_IN ACODEC_VCC ACODEC_GND ACODEC_GND D+ D DIG VPP DIG GNDP SCAN_EN MMC_DATA(GPG[5]) MMC_CMD(GPG[4]) MMC_CLK(GPG[3]) WAKEUP(GPG[2]) IRQ1(GPG[1]) IRQ0(GPG[0]) MEMA19 MEMA18 MEMA17 MEMA16 MEMA15 MEMA14 DIG VCC DIG GNDC MEMA13 MEMA12 MEMA11 MEMA10 MEMA9 MEMA8 MEMA7 MEMA6 MEMA5 DIG VPP DIG GNDP MEMA4 MEMA3
PT8R1202-QFP144
MEMA2 MEMA1 MEMA0 WEB REB UBE(GPB[1]) LBE(GPB[2]) FLASHCSB(GPB[3]) SRAMCSB(GPB[4]) IOCSB0(GPB[5]) IOCSB1(GPB[6]) IOWAIT(GPB[7]) DIG GNDC DIG VCC MEMD15 MEMD14 MEMD13 DIG GNDP DIG VPP MEMD12 MEMD11 MEMD10 MEMD9 DIG GNDC DIG VCC MEMD8 MEMD7 MEMD6 MEMD5 MEMD4 MEMD3 MEMD2 MEMD1 MEMD0 SPLL_GND SPLL_VCC
PT0137(08/04) 9
AUDMCLK(GPD[7]) AUDIN(GPD[8]) DIG GNDP DIG VPP SM_CSB(GPE[0]) SM_CLE(GPE[1]) SM_ALE(GPE[2]) SM_WE(GPE[3]) SM_OE(GPE[4]) SM_RB(GPE[5]) SM_DATA7(GPF[7]) SM_DATA6(GPF[6]) SM_DATA5(GPF[5]) SM_DATA4(GPF[4]) SM_DATA3(GPF[3]) SM_DATA2(GPF[2]) SM_DATA1(GPF[1]) SM_DATA0(GPF[0]) DIG GNDC DIG VCC BTMD0 BTMD1 CLKOUT(GPB[0]) RESET JTAG_TCK(GPC[4]) JTAG_TMS(GPC[5]) JTAG_RST(GPC[6]) JTAG_TDI(GPC[7]) JTAG_TDO(GPC[8]) XTALIN XTALOUT DIG GNDP DIG VPP PLL_SEL PLL_MD1 PLL_MD0
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Ver:4
PT Pericom Technology Inc.
Package Diagram of FPBGA
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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Notes : 1. 2. 3. All dimension are in millimeters. `e' represents the basic solder ball grid pitch. `M' represents the basic solder ball matrix size. And, symbol `N' is the number of balls after depopulating. 4. `b' is measurable at the maximum solder ball diameter after reflow parallel to primary datum -c-. 5. Dimension `aaa' is measured parallel to primary datum -c-. 6. Primary datum -c- and seating plane are defined by the spherical crowns of the solder balls. 7. Package surface shall be matte finish charmilles 24 to 27. 8. Package centering to substrate shall be 0.0760 mm maximum for both X and Y direction respectively. 9. Package warp shall be 0.050mm maximum. 10. Substrate material base is bt resin. 11. The overall package thickness "A" already considers collapse balls. 12. Dimension and tolerancing per ASME Y14.5-1994.
PT0137(08/04) 10
Ver:4
PT Pericom Technology Inc.
Package Diagram for TQFP
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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Notes : 1. 2. 3. 4. All dimension are in millimeters. Dimention shown are nominal with TOL. As indicated. L/F : EFTEC 64T copper or equivalent 0.127mm (.005") thick Foot length "L" is measured at gage plane. At 0.25mm, above the seating plane.
PT0137(08/04) 11
Ver:4
PT Pericom Technology Inc.
I/O Description
Off-chip memory interface
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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The external memory port comprises a 16bit data bus(MEMD[15:0]) and an 20bit address bus(MEMA[19:0]), thus addressing up to 2Mbytes of off-chip code or data. Control signal WEB, REB, and multiple CSB(FLAHSCSB, SRAMCSB, IOCSB0 and IOCSB1) are provided, which make it possible to use a variety of different memories, including flash memory, SRAM and ROM. For SRAM access, UBE and LBE signal support byte access and memory interface block automatically handles control signals for 32bit word, 16bit half-word and 8bit byte access of on-chip microcontroller memory operations. In standard Bluetooth application, only external 256KB flash memory is required in PT8R1202. For additional Bluetooth application including several Bluetooth protocol stack which requires more data memory than internal SRAM of PT8R1202, external SRAM is used for extended data memory of PT8R1202 on-chip microcontroller. The access time of each device can be programmed and the wait cycle ranges 0 to 63 based on system clock, which is normally processor clock, that is CLKSYS. External flash can be programmed via host interface by external host or self update by PT8R1202 on-chip RISC/DSP processor. Because PT8R1202 on-chip RISC/DSP processor is based on harvard architecture, the address map of instruction and data access is difference. Following table 1. shows the instruction address map and table 2. shows the data address map.
Table 4. Instruction address map
Address(24bit)* 0x000000~0x1FFFFF 0x200000~0x3FFFFF 0x400000~0x5FFFFF 0x600000~0x7FFFFF 0x800000~0x9FFFFF Device FLASH SRAM IO0 IO1 Attribute read only read only read only read only Description cacheable, scratch-pad memory or non-cacheable reserved cacheable, scratch-pad memory or non-cacheable cacheable, scratch-pad memory or non-cacheable cacheable, scratch-pad memory or non-cacheable
* This address space is based on byte addressing. There are addition extended two bits in the most significant bits(25th and 24th), and they are used for the indication of section attribute. All instructions are checked whether they are cached in the scratch-pad memory first. Then, those two bits are used to check the source of that instruction fetch. "00" indicates those section can be loaded only through on-chip instruction cache with conventional two-way set associate policy. "01" indicates those section can be loaded only set0 region of on-chip instruction cache. "10" indicates those section can be loaded only set1 region of on-chip instruction cache. "11" indicates those section can be loaded directly from external memory without passing instruction cache. The address space of this internal scratch-pad memory is 0xA00000~0xA0BFFF for XMEM and 0xC00000~0xC0BFFF for YMEM. The scratch memory is divided into four pages each size of which is 32KB with 9-bit instruction tag which consists of 3-bit section attribute and the most significant 6-bit section address. On-chip RISC processor will check the match by full associative comparison with four tag registers of internal scratch-pad memory first. Then, if that tag comparison is matched, instruction will be fetched from internal scratch-pad memory. Otherwise, instruction will be fetch through on-chip instruction cache from external flash memory region.
Table 5. Data address map
Address(23bit)* 0x000000~0x1FFFFF Device FLASH Attribute read/write half-word, word read/write byte, half-word, word read/write byte, half-word, word read/write byte, half-word, word read/write byte, half-word, word DSP memory (14M) read/wrtie byte, half-word, word DSP memory (14M) read/write byte, half-word, word Description instruction code memory constant data memory accessible by on-chip DMA reserved data memory fast fetch instruction code memory accessible by on-chip DMA I/O access accessible by on-chip DMA I/O access accessible by on-chip DMA data memory scratch-pad instruction memory SmartMediaTM FIFO accessible by DMA data memory scratch-pad instruction memory SmartMediaTM FIFO accessible by on-chip DMA data memory Bluetooth baseband FIFO, USB FIFO(0x20C000~0x20FFFF) accessible by on-chip DMA data memory scratch-pad instruction memory
0x200000~0x3FFFFF 0x400000~0x5FFFFF
SRAM
0x600000~0x7FFFFF 0x800000~0x9FFFFF 0xA00000~0xA07FFF
IO0 IO1 XMEM0 (32KB)
0xA08000~0xA0BFFF
XMEM1 (16KB)
0xA0C000~0xA0FFFF
XMEM2 (16KB)
0xC00000~0xC07FFF
YMEM0 (32KB)
read/write byte, half-word, word
PT0137(08/04) 12
Ver:4
PT Pericom Technology Inc.
DSP memory (14M) 0xC08000~0xC0BFFF YMEM1 (16KB) read/write byte, half-word, word DSP memory (14M) read/write byte, half-word, word DSP memory(14M)
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
SmartMediaTM FIFO accessible by on-chip DMA data memory scatch-pad instruction memory SmartMediaTM FIFO accessible by on-chip DMA data memory digital stereo audio output FIFO accessible by on-chip DMA
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0xC0C000~0xC0FFFF
YMEM2 (16KB)
* This address space is based on byte addressing.
Off-chip memory interface waveform diagram
Internal Core Clock (CLKSYS) 0 MEM Wait Cycles Operation Mode CS (Flash, SRAM, I/O) WEB REB UBE LBE MEMA[19:0] unknown ADDR0 ADDR1 MEMD[15:0] 1 MEM Wait Cycles Operation Mode CS (Flash, SRAM, I/O) WEB REB UBE LBE MEMA[19:0] unknown MEMD[15:0]
ADDR0 DATA0 ADDR1 DATA1 ADDR2 DATA2 ADDR3 DATA3 ADDR4 DATA4 MSB ADDR4+1 DATA4 LSB IDLE 8bit-L Read0 16bit Read1 8bit-H Write2 16bit Write3 32bit Read4 IDLE DATA0 DATA1 ADDR2 DATA2 ADDR3 DATA3 ADDR4 ADDR4+1 DATA4 MSB DATA4 LSB ADDR5 DATA5 MSB DATA5 LSB ADDR5+1 IDLE 8bit-L Read0 16bit Read1 8bit-H Write2 16bit Write3 32bit Read4 32bit Write5 IDLE
PT0137(08/04) 13
Ver:4
PT Pericom Technology Inc.
Off-chip memory interface read access timing without wait signal
tRC MEMA[19:0] Address
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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CSB, REB, U/LBE
tRSC Valid Read Data tRDS
RSCYC (0~3) RACYC (1~64)
MEMD[15:0]
tRDH
Off-chip memory interface read access timing with wait signal
tRC MEMA[19:0] Address
CSB, REB, U/LBE
tRSC
WAIT Valid Read Data tRDS
RSCYC (0~3) RWCYC (0~7) RECYC (0~7)
MEMD[15:0]
tRDH
Table 6. Read access timing
Parameter Read cycle time Read data setup time Read data hold time Symbol tRC tRDS tRDH Min 1 (7.8ns) 3 1 Max 64 (500ns) Unit CLKSYS clock cycles (128MHz) ns ns
* RSCYC, RACYC, RWCYC, RECYC based on cycle number of CLKSYS
PT0137(08/04) 14
Ver:4
PT Pericom Technology Inc.
Off-chip memory interface write access timing without wait signal
tWC MEMA[19:0]
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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Address
CSB, WEB, U/LBE
tWSC
tCPW Valid Write Data
tWAH
MEMD[15:0] tWDE tWDS
tWDH
tWDD
WSCYC (0~3)
WACYC (1~64)
WHCYC (0~3)
Off-chip memory interface write access timing with wait signal
tWC MEMA[19:0] Address
CSB, WEB, U/LBE
tWSC
tCPW
tWAH tWAH Valid Write Data
WAIT
MEMD[15:0] tWDE tWDS
tWDH
tWDD
WSCYC (0~3)
WWCYC (0~7)
WECYC (0~7)
WHCYC (0~3)
Table 7. Write access timing
Parameter Write cycle time Write control signal pulse width Write address hold time from control signal Write data output enable time Write data setup time to control signal Write data hold time from control signal Write data output disable time Symbol tWC tCPW tWAH tWDE tWDS tWDH tWDD Min 2 (15.6ns) 1 (7.8ns) 1 (7.8ns) 0 4 1 (7.8ns) 0 Max 65 (507.8ns) 64 (500ns) 1 (7.8ns) Unit CLKSYS clock cycles (128MHz) CLKSYS clock cycles (128MHz) CLKSYS clock cycles (128MHz) ns ns (CLKSYS=128MHz) CLKSYS clock cycles (128MHz) ns
1 (7.8ns)
PT0137(08/04) 15
Ver:4
PT Pericom Technology Inc.
Bluetooth radio interface
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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PT8R1202 supports BlueRFTM RXMODE2/3 Bluetooth radio interface with uni/bi-directional and JTAG/DBUS serial interface .PTI Bluetooth radio transceiver. In RXMODE3, SYNCWORD correlator is located in radio transceiver, SYNCWORD detect signal feeds from external radio transceiver. In RXMODE2, SYNCWORD correlation is processed in PT8R1202, SYNCWORD detect signal feed to external radio transceiver to timing adjustment of modem. In additional to BlueRFTM interface, PT8R1202 supports BlueQTM interface with SBI serial interface.
BlueRF RXMODE3 Radio Transceiver
BlueRF RXMODE2 Radio Transceiver
Correlator and data extraction
BRXD BRXEN BTXEN BPKTCTL BSEN BXTLEN BTXD BPAEN BnPWR BRCLK
RXDATA(GPA4) RXACTIVE(GPA1) TXACTIVE(GPA0) SYNCDETECT(GPA5) GPIO(optional) GPIO(optional) TXDATA(GPA3) TXDATA_EN(GPA2) RFRESET(GPA7) DATACLK(GPA6)
PT8R1202
BRXD BRXEN BTXEN BPKTCTL BSEN BXTLEN BTXD BPAEN BnPWR BRCLK
RXDATA(GPA4) RXACTIVE(GPA1) TXACTIVE(GPA0) SYNCDETECT(GPA5) GPIO(optional) GPIO(optional) TXDATA(GPA3) TXDATA_EN(GPA2) RFRESET(GPA7) DATACLK(GPA6)
DC estimation
Demodulation
DC estimation
Demodulation
PT8R1202
BDCLK BnDEN BMOSI BMISO
BLUERF_TCK(GPA8) BLUERF_TMS(GPA9) BLUERF_TDI(GPA10) BLUERF_TDO(GPA11)
BDCLK BnDEN BMOSI BMISO
BlueRF RXMODE3 - Uni-directional I/F
Register Control I/F
BLUERF_TCK(GPA8) BLUERF_TMS(GPA9) BLUERF_TDI(GPA10) BLUERF_TDO(GPA11)
BlueRF RXMODE2 - Uni-directional I/F
BlueRF RXMODE3 Radio Transceiver
BlueRF RXMODE2 Radio Transceiver
Correlator and data extraction
DC estimation
BPKTCTL BXTLEN BTXD BnPWR BRCLK
SYNCDETECT(GPA5) GPIO(optional) TXDATA(GPA3) RFRESET(GPA7) DATACLK(GPA6)
DC estimation
Demodulation
Demodulation
Register Control I/F
BPKTCTL BXTLEN BTXD BnPWR BRCLK
SYNCDETECT(GPA5) GPIO(optional) TXDATA(GPA3) RFRESET(GPA7) DATACLK(GPA6)
PT8R1202
PT8R1202
Register Control I/F
BDDATA
BLUERF_TDO(GPA11)
Register Control I/F
BDCLK BnDEN
BLUERF_TCK(GPA8) BLUERF_TMS(GPA9)
BDCLK BnDEN BDDATA
BLUERF_TCK(GPA8) BLUERF_TMS(GPA9) BLUERF_TDO(GPA11)
BlueRF RXMODE3 - Bi-directional I/F
BlueRF RXMODE2 - Bi-directional I/F
DC estimation
Demodulation
SYNC_DET
SYNCDETECT(GPA5)
BlueQ Radio Transceiver
RX_TX_DATA
TXDATA(GPA3)
PT8R1202 GDM1202
CLK_REF DATACLK(GPA6)
BlueQ
Register Control I/F
SBCK SBST SBDT
BLUERF_TCK(GPA8) BLUERF_TMS(GPA9) BLUERF_TDO(GPA11)
BlueQ
PT0137(08/04) 16
Ver:4
PT Pericom Technology Inc.
External PCM interface
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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PCMIN, PCMOUT, PCMCLK, PCMSYNC carry one channel of voice data using 8-bit A/u-law, 13-bit /14-bit/16-bit linear PCM at 8kbps. PT8R1202 generates PCMCLK and PCMSYNC as both outputs or input, which can be programmed, and interfaces directly to PCM audio devices. PCMSYNC operates at fixed clock frequency of 8KHz. PCMCLK operates at one of two fixed clock frequencies such as 128 and 256kHz. PCM interface supports both long frame sync signal and short frame sync signal. Additionally, PT8R1202 supports two or four channels of 8-bit A/u-law PCM interfacing with external multi-channel codec. Table 8. Configuration of external PCM interface Configuration Supporting device Qualcomm MSM Motorola MC145481 Oki MSM7717 Oki MSM7704 Oki MSM7705 Motorola MC145483 Oki MSM7716 TBD PCM type A, u-law A, U-law A, U-law A, U-law A, U-law Linear Linear Linear Frame type L S/L L L L S/L L S/L Bit length 8bit 8bit 8bit 8bit 8bit 13bit 14bit 16bit PCMCLK clock 128kHz 128/256kHz 128/256kHz 128/256kHz 256KHz 128/256kHz 128/256kHz 128/256kHz Channel number 1 1 1 2(dual) 4(quad) 1, 2(volume) 1 1
8bit A/u-law codec
13bit linear PCM 14bit linear PCM 16bit linear PCM
PCM_CLK (128, 256, 512, 1024kHz) PCM_SYNC(8kHz) (Short Frame) PCM_SYNC(8kHz) (Long Frame)
8bit
13bit
14bit
16bit
MSB
PCM_IN (sample int at falling edge) PCM_OUT (sample out at rising edge)
8bit A/u-law
LSB LSB LSB LSB 3bit Vol
MSB MSB MSB
13bit linear PCM 14bit linear PCM 16bit linear PCM
PCM_SYNC(8kHz) (Dual-channel)
MSB
PCM_SYNC(8kHz) (Quad-channel)
8bit A/u-law -1Ch
LSB
MSB
8bit A/u-law -2Ch
LSB
MSB
8bit A/u-law -1Ch
LSB
MSB
8bit A/u-law -2Ch
LSB
8bit-3Ch
8bit-4Ch
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External Audio ADC/DAC, SPDIF input interface
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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Audio ADC/DAC interface provides a high quality multi resolution(16/18/20/24-bit) digital audio connection to external audio devices. ADI interface supports I2S audio format as well as optional left-justified or right-justified audio format. ADI interface produces one 64-bit frame at the audio sample frequency using a bit clock and frame sync signal in master mode. In slave mode, ADI accepts one 64-bit frame in audio DAC or one 64/48-bit frame at the audio sample frequency using external generated control signal. ADI interface supports several audio sampling frequency up to 96-kHz such as 32, 44.1, 48, 64, 88.2, or 96-kHz, of which 256 or 384 times main clock can be generated from on-chip audio PLL or external clock signal by interface mode programming. ADI interface contains dual on-chip FIFO which size contains maximally 2048 samples with 16-bit or 1024 samples with above 16-bit stereo audio data through YMEM2 shared with RISC/DSP processor. Table 9. Audio interface pin description
Pin Name AUDMCLK AUDSCLK I/O programmable programmable Type clock clock Description audio oversampled clock This clock can be programmed 256 or 384 times AUDLRCLK audio serial data bit clock This clock is fixed at 64 times AUDLRCLK in output, but can be programmed at 64 or 48 times AUDLRCLK or UARTRTS in input audio frame synchronization clock This clock can be programmed up to 96kHz audio serial data used for sending playback data to DAC audio serial data used for receiving recording data from ADC SPDIF serial data input audio input serial data bit clock This pin can be programmed as alternative audio serial data bit clock for audio input interface audio input frame synchronization clock This pin can be programmed as alternative audio frame synchronization for audio input interface
AUDLRCLK AUDOUT AUDIN UARTRTS UARTCTS
programmable output input programmable programmable
clock serial data serial data clock clock
* I2S interface
AUDSCLK AUDLRCLK AUDOUT
MS
MS-1 MS-2
Left
2 1 LS MS
MS-1 MS-2
Right
2 1 LS
Audio Output : 32 AUDBCLK Audio Input : Any(24, 32) AUDBCLK
* Left-justified interface
AUDSCLK AUDLRCLK AUDOUT
MS
MS-1 MS-2
Left
2 1 LS MS
MS-1 MS-2
Right
2 1 LS
Audio Output : 32 AUDBCLK Audio Input : Any(24, 32) AUDBCLK
* Right-justified interface
AUSCLK AUDLRCLK AUDOUT
MS
Left
MS
MS-1 MS-2
Right
2 1 LS MS MS
MS-1 MS-2
2
1
LS
Audio Output : 32 AUDBCLK Audio Input : 24, 32 AUDBCLK
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SPDIF interface
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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The PT8R1202 supports IEC-958 or SPDIF serial digital input or output data directly. Through SPDIF interface, uncompressed audio PCM or compressed PCM can be transferred into or from the PT8R1202 in order to do wireless audio streaming solution. The function of SPDIF and I2S input shall be executed in the time share way. The function of SPDIF and I2S output can be executed in the same time. Following figure shows the supported data format in the PT8R1202.
0 34 78 Preamble Aux Data LSB
Audio Data Sub-frame
27 31 MSB V U C P
Validity User Data Channel Status Data Parity Bit Sub-frame X Channel A Y Channel B Z Channel A Y Sub-frame Channel B X Channel A Y Channel B
Frame 191
Frame 0 Start of Channel Status Block
Frame 1
USB interface USB controller in PT8R1202 is compliant USB 1.1 version. The USB functionality is executed by an USB hardware block and firmware running on V6 RISC processor. This configuration allows acceleration of the intensive function processing while allowing flexibility in the implementation of higher level protocols over USB. USB controller in PT8R1202 supports both 12Mbps high speed mode and 1.5Mbps low speed mode and host and device mode programmed by firmware. The USB hardware block consists of a serial interface engine(SIE), a serial bus controller(SBC) and a V6PB bus interface. The SIE performs the clock/data separation, NRZI encoding and decoding, bit stuffing and unstuffing, CRC generation and checking and the serial-parallel data conversion. The SBC consists of protocol engine and a USB device with nine endpoints including endpoint0 for control, each with single or double buffered scheme. Control endpoint consists of single 16-byte FIFO for transmit and receive, and eight endpoints consist of dual 64-byte FIFOs in each side, which is shared through XMEM2 with on-chip RISC processor. Four of eight endpoints are for transmit and others for receiving. Additionally, there are four endpoints dedicated to isochronous operation with 1023-byte FIFO located in XMEM2. The SBC manages the device address, monitors the status of the transactions, manage the FIFOs and communicates to the processor through a set of status and control registers. The V6PB bus interface connects the serial bus controller to the processor. Endpoint 0 (EP0) : Control Endpoint equipped with 16bytes single-buffered FIFO Endpoint 1 (EP1) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO Endpoint 2 (EP2) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO Endpoint 3 (EP3) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO Endpoint 4 (EP4) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO Endpoint 5 (EP5) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO Endpoint 6 (EP6) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO Endpoint 7 (EP7) : OUT Endpoint (isochronous) with 1023bytes single-buffered FIFO Endpoint 8 (EP8) : IN Endpoint (isochronous) with 1023bytes single-buffered FIFO Endpoint 9 (EP9) : OUT Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO Endpoint 10 (EP10) : IN Endpoint (control, interrupt, bulk) with 64bytes double-buffered FIFO Endpoint 11 (EP11) : OUT Endpoint (isochronous) with 1023bytes single-buffered FIFO Endpoint 12 (EP12) : IN Endpoint (isochronous) with 1023bytes single-buffered FIFO
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Table 10. Recommend Endpoint mapping in USB
End point Bluetooth USB dongle Bluetooth USB dongle + USB storage device Common control BT Event (interrupt) BT Command (control) BT ACL data (Bulk) BT ACL data (Bulk) HUB reserved BT SCO data (Isoch) BT SCO data (Isoch) USB storage (Bulk) USB storage (Bulk) reserved reserved
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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PT8R1202 supports device function, Hub function and host function in USB 1.1 version. Specially, PT8R1202 emulates the multiple device operations simultaneously with supporting Hub function. Together with on-chip Nand flash controller and audio DSP, PT8R1202 supports multiple function in USB dongle which integrates Bluetooth, USB storage device and USB sound card. Following list is possible configuration for multiple USB device system on a chip.
EP0 EP1(Out) EP2(In) EP3(Out) EP4(In) EP5(Out) EP6(In) EP7(Out) EP8(In) EP9(Out) EP10(In) EP11(Out) EP12(In)
Common control BT Event (interrupt) BT Command (control) BT ACL data (Bulk) BT ACL data (Bulk) reserved reserved BT SCO data (Isoch) BT SCO data (Isoch)
reserved reserved
Bluetooth USB dongle + USB storage device + USB sound device Common control BT Event (interrupt) BT Command (control) BT ACL data (Bulk) BT ACL data (Bulk) HUB USB audio control BT SCO data (Isoch) BT SCO data (Isoch) USB storage (Bulk) USB storage (Bulk) USB audio stream (Isoch) USB audio stream (Isoch)
Wireless Stereo Headset Bluetooth over Bluetooth Bulk, ISO device Bulk, ISO device Bulk device ISO device
USB Hub Bluetooth Device Driver Portable Storage Device Driver Audio Device Driver
USB Bus
(Multiple USB devices over single USB bus) PT8R1202
NAND
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PT Pericom Technology Inc.
UART interface
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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UARTTX, UARTRX, UARTRTS, and UARTCTS form a conventional asynchronous data serial port. The interface is designed to operate correctly when connected to other UART devices such as NS16550A. The signaling levels are 0V and 3.3V. The interface is programmable over a variety of bit rates. It supports many configurations such as no, even or odd parity, one or two stop bit, number of bit in a frame, break conditions, and hardware flow control on or off. The maximum UART data rates is 1.8Mb/s. Two-way hardware control is implemented by UARTRTS and UARTCTS. If input UARTCTS signal becomes high, transmission will be stopped, else it will be continued. If internal UART FIFO will be full, output UARTRTS signal becomes high, else becomes low. Flash Card interface PT8R1202 supports two types of flash card such as SmartMediaTM flash devices and MMC or SDCard flash devices. This flash card devices are small removable cards that contain one or two NAND Flash devices. Alternatively, the system designer can use non-removable NAND flash chips. PT8R1202 supports hardware interface logic for SmartMediaTM devices, but only supports software firmware using GPIO for MMC or SDCard. The SmartMediaTM electrical interface uses an 8-bit data/address bus and 6-bit control lines. PT8R1202 supports up to 4GB SmartMediaTM devices.
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JTAG interface
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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PT8R1202 supports IEEE1149.1 standard specification compliant interface. This interface supports basic test commands such as EXTEST, SMAPLE, BYPASS, and IDCODE. Beside of this, JTAG interface can be used communication channel with PTI enhanced on-chip hardware debugger controller. Using on-chip debugger controller, off-chip debug handler or external host can access internal peripheral device registers, external memory interface, and executes real-timing hardware debugging and monitoring of on-chip embedded RISC processor. Also, external host can communicate on-chip RISC processor through JTAG with on-chip hardware managed channel buffer. There are sixteen debug registers specified and these will be used in PTI own development chip manager software, named as V6EMUTM. The length of instruction register in JTAG interface is 6bit and that of debug data register is 32bit. Table 11. shows the summary of TAP instructions supported in PT8R1202 and Table 12. shows the summary of debugger registers in JTAG interface. Table 11. TAP instructions
Instruction EXTEST Opcode 0x000000 Description EXTEST initiates testing of external circuitry, typically board-level interconnects and off chip circuitry. EXTEST connects the Boundary-Scan register between TDI and TDO in the SHIFT_DR state only. When EXTEXT is selected, all output signal pin values are driven by values shifted into the Boundary-Scan register and may change only on the falling-edge of TCK in the Update_DR state. Also, when EXTEST is selected, all system input pin states must be loaded into the Boundary-Scan register on the rising-edge of TCK in the Capture_DR state. Values shifted into input latches in the Boundary-Scan register are never used by the processor's internal logic. SAMPLE / PRELOAD performs two functions: * When the TAP controller is in the Capture-DR state, the SAMPLE instruction occurs on the rising edge of TCK and provides a snapshot of the component's normal operation without interfering with that normal operation. The instruction causes Boundary-Scan register cells associated with outputs to SAMPLE the value being driven by or to the processor. * When the TAP controller is in the Update-DR state, the PRELOAD instruction occurs on the falling edge of TCK. This instruction causes the transfer of data held in the Boundary-Scan cells to the slave register cells. Typically the slave latched data is then applied to the system outputs by means of the EXTEST instruction. IDCODE is used in conjunction with the device identification register. It connects the identification register between TDI and TDO in the Shift_DR state. When selected, IDCODE parallel-loads the hard-wired identification code (32 bits) on TDO into the identification register on the rising edge of TCK in the Capture_DR state. NOTE: The device identification register is not altered by data being shifted in on TDI. DEBUG instruction select the DEBUGReg with address indicator SSSS. * When the TAP controller is in the Capture-DR state, the DEBUG instruction occurs on the rising edge of TCK and executes a snapshot of DEBUG register addressed SSSS into DEBUGReg. * When the TAP controller is in the Update-DR state, the DEBUG instruction occurs on the falling edge of TCK. This instruction causes the transfer of data held in DEBUGReg to DEBUG register addressed SSSS. BYPASS instruction selects the Bypass register between TDI and TDO pins while in SHIFT_DR state, effectively bypassing the processor's test logic. 0 is captured in the CAPTURE_DR state. While this instruction is in effect, all other test data registers have no effect on the operation of the system. Test data registers with both test and system functionality perform their system functions when this instruction is selected
SAMPLE
0x000001
IDCODE
0x011111
DEBUG (Private Instruction)
0x10SSSS
BYPASS
0x111111
Table 12. Debug interface register address map
Address 0x0 0x1 0x2 0x3 0x4 0x5 0x7 0x9 0xA 0xB Name DEBUG_CMD DEBUG_CTRL DEBUG_TX DEBUG_RX DEBUG_ADDR DEBUG_WDATA0 (DEBUG_CYC_CNT) DEBUG_RDATA0 DEBUG_INST_ACNT DEBUG_INST_SCNT DEBUG_BREAK_PC Attribute Write Read Read Write Write Write Read Read Read Write Description debugger control register debug handler control register debug handler transmit register debug handler receive register debugger address register debugger write data register0(31:0) debugger instruction step count debugger read data register0(31:0) debugger instruction cycle accumulator debugger instruction step cycle count debugger breakpoint PC register
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Electrical specifications
Absolute Maximum Rating
Symbol TA Parameter Storage Temperature Supply Voltages : SPLL_VCC, APLL_VCC, VCC Supply Voltage : ACODEC_VCC Supply Voltage : VPP Other Terminal Voltage TA= +25C Condition
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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Min -40 -0.4 -0.4 -0.4 -0.4
Typ
Max 150 2.1 3.6 3.6 3.6
Unit C V V V V
Recommended Operating Conditions
Symbol TA VCC VPP SPVCC APVCC ACVCC Parameter Ambient Temperature Supply Voltage VCC (to VCC_GND)* Supply Voltage VPP (to VPP_GND)* Supply Voltage SPLL_VCC (to SPLL_GND)* Supply Voltage APLL_VCC (to APLL_GND)* Supply Voltage ACODEC_VCC(to ACODEC_GND)* Difference between any two VCC, SPLL_VCC, APLL_VCC terminals TA= +25C TA=+25C TA=+25C TA=+25C TA=+25C TA=+25C Condition Min -40 1.62 2.7 1.62 1.62 2.7 Typ 25 1.8 3.0 1.8 1.8 3.0 Max 105 1.98 3.6** 1.98 1.98 3.6 0.3 Unit C V V V V V V
* An external regulator is required for reliability
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DC/AC Specification
Sym Parameter Condition Digital Inputs VIH VIL ILEAK Logical input High Logical input Low Input leakage current 0.5 < VIN < VCC-0.5
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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Unless otherwise noted, the specification applies for: TA=+25C, Typical conditions
Min Typ Max Unit
2.0 -0.3 -1
VPP 0.8 1
V V A
Digital Outputs VOH VOL Logical output High Logical output Low Tri-state output leakage current Low level max output current for MEMA, MEMD, REB, WEB High level max output current for MEMA, MEMD, REB, WEB Low level max output current for others High level max output current for others USB Signals (D+, D-) VDI VCM VSE VUOL VUOH IUOZ Differential input sensitivity Differential common mode range Single ended receiver threshold Output low voltage Output high voltage Tri-state date line leakage RL=1.5K RL=1.5K O < VIN < 3.3 2.8 -10 10 (D+) - (D-) -0.2 0.8 0.7 0.2 2.5 1.7 0.3 V V V V V A -1 13.2 24.8 6.6 12.4 2.4 0.4 1 V V A mA mA mA mA
Current Consumption Operating supply current of VCC Low power mode supply current of VCC Sleep mode supply current of VCC Operating supply current of VPP Sleep mode supply current of VPP Operating supply current of SPLL_VCC Sleep mode supply current of SPLL_VCC Operating supply current of APLL_VCC Sleep mode supply current of APLL_VCC Operating supply current of ACODEC_VCC Sleep mode supply current of ACODEC_VCC System Power Consumption Deep sleep with RTC timer operation Sleep with RTC timer operation BT data transfer (DM5)* BT voice connection (HV1)* MP3 decoding from NAND flash* MP3(128kbps) streaming from Bluetooth link* SBC(384kbps) streaming from Bluetooth link* VOIP(G.723.1) call with Bluetooth link* VPP, ACODEC_VCC =3.0V, others all 1.8V VPP, ACODEC_VCC =3.0V, others all 1.8V VPP, ACODEC_VCC =3.0V, others all 1.8V VPP, ACODEC_VCC =3.0V, others all 1.8V VPP, ACODEC_VCC =3.0V, others all 1.8V VPP, ACODEC_VCC =3.0V, others all 1.8V VPP, ACODEC_VCC =3.0V, others all 1.8V VPP, ACODEC_VCC =3.0V, others all 1.8V 4.7 18.2 41 45 111 139 91 136 mW mW mW mW mW mW mW mW under oscillator operation under 96MHz operation under IDLE operation 100 3.5 0.55 10 0.5 3.5 0.35 1.6 0.2 11.8 0.12 mA mA mA mA mA mA mA mA mA mA mA
* The actual power consumption depends on real situation.
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Application Note
PT8R1202 reference configuration
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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13MHz 16MHz
1.8V LDO
3.3V LDO
XTALIN
Bluetooth Radio Transceiver
RESET TXACTIVE RXACTIVE TXDATAEN TXDATA RXDATA SYNCDETECT DATACLK TCK TMS TDI TDO
RESET TXACTIVE(GPA0) RXACTIVE(GPA1) TXDATAEN(GPA2) TXDATA(GPA3) RXDATA(GPA4) SYNCDETECT(GPA5) DATACLK(GPA6) BLUERF_TCK(GPA8) BLUERF_TMS(GPA9) BLUERF_TDI(GPA10) BLUERF_TDO(GPA11)
FLASHCSB SRAMCSB IOCSB0/1 IOWAIT MEMA[19:0] WEB,REB,UBE,LBE MEMD[15:0] PCMCLK, PCMSYNC, PCMIN, PCMOUT EARA
XTALOUT
XTALIN
NOR Flash
SRAM
LCD Compact Flash Ethernet IDE
PCM Codec (MC145483)
32.768kHz EARB AUDSCLK, AUDLRCLK, AUDOUT, AUDMCLK, AUDIN, GPIO(SCL), GPIO(SDA) SM_CSB,CLE,ALE SM_WE,OE,RB SM_DATA[7:0] GPIOs GPG0(KEY0), GPG1(KEY1), GPG2(KEY2)
GDM1002 PT8R1002
USB PC serial port PC Parallel port
RS232 driver
Audio DAC (CS42L50)
D+ DUARTTX,UARTRX, UARTRTS,UARTCTS JTAG_TCK,JTAG_TMS, JTAG_TDI,JTAG_TDO, JTAG_RST
Nand Flash
MMC/SD card
Applications
Wireless speaker for DVD / PC surround speaker with CD quality, low-latency audio transmission Portable digital audio player with Bluetooth streaming and storage function Bluetooth stereo headset with combining A/V profile and headset profile 3-in-one multi-functions(Bluetooth, USB audio, USB flash storage) USB dongle Bluetooth USB printer adaptor with USB host function Bluetooth handsfree with on-chip echo cancellation function Bluetooth VOIP phone with on-chip speech compression function
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Notes
Data Sheet PT8R1202 Bluetooth Digital Audio Streaming IC
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Pericom Technology Inc.
Email: support@pti.com.cn China: Web Site: www.pti.com.cn, www.pti-ic.com No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Asia Pacific: Fax: (86)-21-6485 2181
Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667
U.S.A.:
3545 North First Street, San Jose, California 95134, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.
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